1. Field of the Invention
The present invention relates to a test circuit for semiconductor devices and more specifically to a test circuit for a plurality of monitor TEGs (Test Element Groups) that monitors variations in process parameters in a semiconductor chip.
2. Discussion of the Background
With advances in manufacturing processes for miniaturization and high integration of semiconductor devices, reducing device parameter deviations within wafers and within chips due to process parameter variations has become an important problem in the improvement of semiconductor device manufacturing yields.
Conventionally, for process parameter monitoring, in-wafer TEGs (Test Element Groups), dicing line TEGs (TEGs in dicing line regions), and in-chip discrete element TEGs have been employed. However, they are insufficient as monitor TEGs for evaluating variations in process parameters for each chip. In view of monitoring process parameter variations within a chip, the demand has increased for a monitor TEG test circuit that allows process parameter variations to be evaluated with precision.
Here, the process parameter monitoring is to monitor deviations of characteristics of components of semiconductor devices from their design values due to variations in process parameters. The components to be monitored include discrete components, such as diffused resistors, diodes, transistors, etc., circuits, such as inverters, ring oscillators, etc., wiring TEGs each consisting of a group of contact holes and cross-over wirings, and so on.
The monitor TEGs are tested mainly in the middle of wafer processing in order to locate as early as possible faults due to variations in processing conditions. The wafer is diced into chips and the resultant chips are sealed in packages. After that, using an LSI tester good ones are selected out of packaged semiconductor devices and then shipped.
The causes of faults found after packaging are analyzed using an SEM (Scanning Electron Microscope) with the packages opened and then used to improve the manufacturing process. However, such a conventional destructive fault analysis method involves much time and effort. The fact is that effective feedback of fault data due to variations in wafer processing is considerably difficult.
That is, the main objective of the conventional monitor TEG-based intermediate testing in the wafer processing is to detect variations in the wafer processing as early as possible and contribute to the improvement of the manufacturing process.